1. Field of the Invention
The present invention relates to a semiconductor substrate, manufacturing method therefor, and semiconductor device and, more particularly, to a semiconductor substrate including, e.g., regions with different strained states in a surface layer, i.e., a strained semiconductor region and unstrained semiconductor region, a manufacturing method therefor, and a semiconductor device using the semiconductor substrate.
2. Description of the Related Art
In a strained silicon under tensile stress, it is known that mobility of electrons in Si increases due to the effect of internal stress in the strained Si layer. The strained Si layer is defined as an Si layer whose lattice constant deviates from an original Si lattice constant owing to the stress. An Si layer without stress having an original Si lattice constant will be called as a relaxed Si layer, compared to the strained Si layer. Also for silicon germanium (SiGe) to be described later, an SiGe layer with stress will be called a strained SiGe layer, and an SiGe layer without stress will be called as a relaxed SiGe layer.
The operation speed of a semiconductor device can be increased when the device is formed using, e.g., a strained Si layer with tensile stress for a channel of an n-channel metal-oxide semiconductor field effect transistor (MOSFET: to be referred to as an nMOS hereinafter). A high-performance, advanced-function semiconductor device can be manufactured by embedding semiconductor devices with various functions on a strained Si substrate having a strained Si layer.
Although the electron mobility increases in an Si layer under tensile stress, but the hole mobility becomes equal to or lower than that in the bulk Si. Strained Si is therefore suitable for an nMOS in terms of semiconductor device characteristics. A pMOS favors strained SiGe which is higher in hole mobility than Si. In this situation, a semiconductor substrate having two semiconductor regions with different strained states has been proposed. An example of the substrate is shown in FIGS. 18A and 18B.
This example employs a strained silicon on insulator (SOI) substrate 3 (FIG. 18A) having a thin strained Si layer 21 formed above a substrate 1 and a buried oxide film (BOX) layer 11 and relaxed SiGe layer 12 without stress which are sandwiched between the strained Si layer 21 and the Si substrate 1. In this semiconductor substrate, a relaxed Si region B having a relaxed Si layer 22 without stress is formed on part of the substrate surface while a strained Si region A having the strained Si layer 21 remains in the rest of the surface.
The relaxed Si region B can be formed as follows. First, the entire surface is thermally oxidized to form an oxide film (SiO2 film), and the strained Si layer 21 in the region B is exposed by patterning. In the region B, the Si substrate 1 is exposed by selectively removing the exposed strained Si layer 21, relaxed SiGe layer 12, and BOX layer 11. A relaxed Si layer 22 without stress is formed on the Si substrate 1 by selective epitaxial growth, then the SiO2 film on the strained Si layer 21 surface is removed. In this manner, a semiconductor substrate having the strained Si region A whose surface is the strained Si layer 21 and the relaxed Si region B whose surface is the relaxed Si layer 22 without stress is formed, as shown in FIG. 18B.
In a process of manufacturing a semiconductor substrate having the strained Si region A and relaxed Si region B by selective epitaxial growth, for example, with the structure shown in FIG. 18B, annealing at a relatively high temperature such as thermal oxidization or hydrogen annealing is generally performed before selective epitaxial growth. The annealing generates misfit dislocations near an interface between the strained Si layer 21 and the relaxed SiGe layer 12 due to the difference between their lattice constants, thereby relaxing the strain of the strained Si layer 21. Thermal oxidization of the thin strained Si layer 21 makes the layer 21 thinner, and also makes it difficult to control the thickness of the strained Si layer 21, exactly.
During the annealing, Ge diffuses from the relaxed SiGe layer with high Ge concentration into the strained Si layer 21 formed on the relaxed SiGe layer. As a result, the strain of the strained Si layer 21 decreases, failing to sufficiently increase the electron mobility.
Another example is a semiconductor substrate having a strained Si region A and relaxed Si region B by using a strained Si substrate 2, as a starting material, in which a strained Si layer 21 is formed on an SiGe buffer layer 31 on an Si substrate 1, as shown in FIG. 19A. In the SiGe buffer layer 31, its Ge concentration is low in a portion close to the Si substrate 1 in order to suppress the generation of above-mentioned misfit dislocations, and gradually increases toward the surface.
In this example, the relaxed Si region B is formed as follows. First, part of the strained Si layer 21 is covered with a mask, and the relaxed Si region B being formed an Si layer without stress is exposed. Then, the strained Si layer 21 and SiGe buffer layer 31 in the region B are selectively etched away to expose the surface of the unstrained Si substrate 1. The exposed surface is defined as the relaxed Si region B, as shown in FIG. 19B. In this structure, a step is formed between the strained Si region A on the SiGe buffer layer 31 and the relaxed Si region B from which the SiGe buffer layer 31 is removed.
As described above, the SiGe buffer layer 31 is a so-called graded SiGe layer in which the Ge concentration in Si is not uniform in the direction of thickness, lower near the Si substrate 1, and gradually higher toward the surface. In manufacturing a semiconductor substrate with the structure shown in FIG. 19B, the SiGe buffer layer 31 is etched away, as described above. However, since the Ge concentration in the SiGe buffer layer 31 near the Si substrate 1 is low, the selectivity in the etching between the SiGe buffer layer 31 and Si substrate 1 becomes low, failing to control the etching amount. Consequently, the etching uniformity in a wafer, between wafers and among lots becomes worse, and the level of the relaxed Si region B becomes nonuniform.
When a semiconductor device is manufactured using a semiconductor substrate suffering the above problems, for example, planarization becomes difficult in the manufacturing process due to the step of the substrate, and desired patterning is hardly achieved. The characteristics of manufactured semiconductor devices vary owing to, e.g., variations in the thickness of the strained Si layer 21 in the surface or variations in the Ge concentration of the SiGe layer 12 in contact with the strained Si layer 21, failing to obtain desired characteristics.
The SiGe buffer layer 31 contains many misfit dislocations in order to relax the difference in lattice constant between the Si substrate 1 and the SiGe buffer layer 31. When a deep semiconductor element, e.g., a trench memory cell, is formed in the strained Si region A having misfit dislocations, the trench may cross the misfit dislocation. The dislocation acts as a current leakage path, and the element characteristics is degraded by an increased leakage current.
In order to manufacture a semiconductor device with excellent desired characteristics, a semiconductor substrate must be obtained in which (1) the entire substrate is flat without any step between the strained Si region and the relaxed Si region, (2) the strained Si layer and relaxed Si layer, in which semiconductor elements are to be formed, are uniform in, for example, the thicknesses and impurity concentrations, and (3) lattice defects such as misfit dislocations do not exist in a trench formation region in the substrate.